DESIGN SERVICE

디자인 서비스

Degisn Service Model

Level 0 Prime :
Spec feasibility to Sample 제작지원 단계
  • Spec Define/Verification
  • Test / IQ (양산지원 / 불량분석)
  • Include Level 0
Level 1 :
RTL Interface to Sample
제작지원 단계
  • Top Integration
  • Synthesis
  • RTL to Gate Equivalence Check
  • Function Mode STA
  • Clock Generation Module Design
  • DFT RTL Design
  • Include Level 1.5
Level 2 :
Netlist Interface to Sample 제작지원 단계
  • Checking DFT Logic for Gate-level Netlist
  • Include Level 2.5
Level 3 :
PG to Sample
제작지원 단계
  • Physical Verification
  • Design Preparation for Fab
  • Making Ebeam Data
Level 0 :
Spec Interface to Sample
제작지원 단계
  • Top Integration
  • Bus Architecture Design
  • System Level Verification
  • Test Firmware Suite
  • IP Design, IP Introduction, IP Verification
  • Block Design/Verification
  • FPGA System Design/Emulation
  • Include Level 1
Level 1.5 :
Netlist Interface to Sample 제작지원 단계 with DFT
  • RTL Design For Test (Logic/Memory/IP/IO etc) Design
  • DFT Mode STA/Simulation
  • DFT Vector Generation
  • DFT to Gate Equivalence Check
  • Include Level 2
Level 2.5 :
Layout to PG
(Pattern Generation)
  • Place & Route (P&R)
  • Manual(MOS제품), Mixed(Analog제품)
  • Physical Verification
  • Post Layout STA
  • Layout to Gate Equivalence Check
  • Include Level 3

Edge Service

SoC Support
  • Spec Defition for Mass Production
  • Top Integration for DFT
  • Suggestion Tech. Process
RTL Check
  • Linting & Optimization
  • Test Design Rule Check
  • Layout Guide
Design Review Organizer
  • Design Methodology Review
  • Pre-Layout Design Review
  • Post-layout Design Review
Synthesis for Timing Closure
  • Synthesis for Power Optimization
  • Static Timing Analysis
  • Equivalence Check
Auto P&R
  • Early Engagement
  • PowerPlan/FloorPlan
  • CTS/CTO
  • Chip Size Optimization
  • P&R
  • Timing Optimization
Design Review Organizer
  • Analog IC/IP
  • Digital CMOS Logic
  • Mixed Device
  • Memory Device
  • LDI
  • EEPROM
Design For Testability
  • Scan Design & ATPG
  • Memory BIST/BIRA
  • At-Speed Test Strategy
Verification & Post Processing
  • Multi-Power LVS
  • Physical Design Rule Check
  • Noise Analysis
  • IR-Drop/Rise Analysis
  • Bonding Rule Check
  • Antenna Rule
  • Check

서비스 강점

제품개발이 동시에 가능한 Man Power

  • 삼성전자 파운드리 협력사
  • 원스톱 지원체계 구축 (RTL to GDS handoff)
  • SoC / DFT 전담팀 운용
  • 제품 최적화 솔루션 제공

1

다양한 공정/과제 진행 경험

  • 많은 경험을 토대로 Hight Quality 디자인 서비스 제공
  • 130nm~7nm 개발 경험
  • Design Verification 진행
  • DFT 과제 진행

1

완벽한 보안 시스템운영

  • 사각지대 없는 CCTV 모니터링
  • 고객사별 네트워크/Office 분리
  • 연중무휴 경비인력 상주
  • 스마트폰, USB등 모든 입출력 장치 봉인 및 통제

프로젝트 수행

2018

12

10nm SSD Controller Project(1) Design Win

2019

05

14nm SSD Controller Project(2) Design Win

05

DFT Dedicated

05

10nm SSD Controller Project(1) GDS release

07

Design Verification Design Win